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Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS CLOCK GENERATOR
FEATURES
* 10 single ended LVCMOS outputs, 7 typical output impedance * Selectable CLK0 and CLK1 LVCMOS clock inputs * CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL * Maximum input/output frequency: 150MHz * Output skew: 350ps (maximum) * 3.3V input, 3.3V outputs * -40C to 85C ambient operating temperature * Pin compatible to the MPC946
ICS87946I
GENERAL DESCRIPTION
The ICS87946I is a low skew, /1, /2 LVCMOS Clock Generator and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS87946I has two selectable single ended clock inputs. The single ended clock inputs accept LVCMOS or LVTTL input levels. The low impedance LVCMOS outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 10 to 20 by utilizing the ability of the outputs to drive two series terminated lines.
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The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the /1, /2 or a combination of /1 and /2 modes. The master reset input, MR/nOE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs. The ICS87946I is characterized at 3.3V core/3.3V output. Guaranteed output and part-to-part skew characteristics make the ICS87946I ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK_SEL CLK0 CLK1 DIV_SELA 0 QB0:QB2 1 DIV_SELB 0 QC0:QC3 1 DIV_SELC MR/nOE 0 1 /1 /2 0 QA0:QA2 1
PIN ASSIGNMENT
MR/nOE GND GND VDDA VDDA QA0 QA1 QA2
32 31 30 29 28 27 26 25 CLK_SEL VDD CLK0 CLK1 DIV_SELA DIV_SELB DIV_SELC GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VDDC QC0 GND QC1 VDDC QC2 GND QC3
24 23 22
GND QB0 VDDB QB1 GND QB2 VDDB VDDC
ICS87946I
21 20 19 18 17
32-Lead LQFP 7mm x 7mm x 1.4mm Y Package Top View
87946AYI
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1
REV. B OCTOBER 22, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS CLOCK GENERATOR
Type Input Power Input Input Input Input Power Power Output Description Clock select input. When HIGH, selects CLK1. When LOW, Pulldown selects CLK0. LVCMOS / LVTTL interface levels. Positive supply pins. LVCMOS / LVTTL clock inputs. Controls frequency division for Bank A outputs. Pulldown LVCMOS / LVTTL interface levels. Controls frequency division for Bank B outputs. Pulldown LVCMOS / LVTTL interface levels. Controls frequency division for Bank C outputs. Pulldown LVCMOS / LVTTL interface levels. Power supply ground. Positive supply pins for Bank C outputs. Pullup
ICS87946I
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3, 4 5 6 7 8, 11, 15, 20, 24, 27, 31 9, 13, 17 10, 12, 14, 16 18, 22 Name CLK_SEL VDD CLK0, CLK1 DIV_SELA DIV_SELB DIV_SELC GND VDDC QC0, QC1, QC2, QC3 VDDB
Bank C outputs. LVCMOS / LVTTL interface levels. 7 typical output impedance. Power Positive supply pins for Bank B outputs. Bank B outputs. LVCMOS / LVTTL interface levels. 19, 21, 23 QB2, QB1, QB0 Output 7 typical output impedance. 25, 29 VDDA Power Positive supply pins for Bank A outputs. 26, 28, Bank A outputs. LVCMOS / LVTTL interface levels. QA2, QA1, QA0 Output 30 7 typical output impedance. Master reset and output enable When LOW, output drivers are 32 MR/nOE Input Pulldown enabled. When HIGH, output drivers are in HiZ and dividers are reset. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output); NOTE 1 Output Impedance 51 51 VDD, VDDx = 3.6V 25 7 Test Conditions Minimum Typical Maximum 4 Units pF K K pF
NOTE 1: VDDx denotes VDDA, VDDB, VDDC.
TABLE 3. FUNCTION TABLE
MR/nOE 1 0 0 0 0 0 0
87946AYI
DIV_SELA X 0 1 X X X X
Inputs DIV_SELB X X X 0 1 X X
DIV_SELC X X X X X 0 1
QA0:QA2 Hi Z fIN/1 fIN/2 Active Active Active Active
Outputs QB0:QB2 Hi Z Active Active fIN/1 fIN/2 Active Active
QC0:QC3 Hi Z Active Active Active Active fIN/1 fIN/2
REV. B OCTOBER 22, 2002
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2
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS CLOCK GENERATOR
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDx + 0.5V 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ICS87946I
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VDD Outputs, VDDx Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDX = 3.3V0.3V, TA = -40C TO 85C
Symbol VDD VDDx IDD Parameter Positive Supply Voltage Output Supply Voltage; NOTE 1 Power Supply Current Test Conditions Minimum 3.0 3.0 Typical 3.3 3.3 Maximum 3.6 3.6 85 Units V V mA
NOTE 1: VDDx denotes VDDA, VDDB, VDDC.
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = VDDX = 3.3V0.3V, TA = -40C TO 85C
Symbol Parameter DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL, MR/nOE CLK0, CLK1 DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL, MR/nOE CLK0, CLK1 DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL, MR/nOE CLK0, CLK1 DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL, MR/nOE CLK0, CLK1 Test Conditions Minimum 2 2 -0.3 -0.3 VDD = VIN = 3.6V VDD = VIN = 3.6V VDD = 3.6V, VIN = 0V VDD = 3.6V, VIN = 0V IOH = -20mA IOL = 20mA -5 -120 2.5 0.4 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 120 5 Units V V V V A A A A V V
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
IIL VOH VOL
Input Low Current
Output High Voltage Output Low Voltage
87946AYI
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3
REV. B OCTOBER 22, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS CLOCK GENERATOR
Test Conditions Minimum 150 2 2 12.0 11.5 350 fMAX < 100MHz fMAX > 100MHz 0.8V to 2.0V 0.8V to 2.0V 0.1 0.1 350 450 4.5 1.0 1.0 11 Typical Maximum Units MHz ns ns ps ps ps ns ns ns ns ns
ICS87946I
TABLE 5. AC CHARACTERISTICS, VDD = VDDX = 3.3V0.3V, TA = -40C TO 85C
Symbol fMAX tpLH tpHL Parameter Input Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Output Skew; NOTE 2, 6 Multiple Frequency Skew; NOTE 3, 6 Par t-to-Par t Skew; NOTE 4, 6 Output Rise Time; NOTE 5 Output Fall Time; NOTE 5 Output Enable Time; NOTE 5
tsk(o) tsk(w) tsk(pp)
tR tF tEN
Output Disable Time; NOTE 5 11 tDIS NOTE 1: Measured from the VDD/2 of the input to VDDx/2 of the output. NOTE 2: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. Measured at VDDx/2. NOTE 3: Defined as skew across banks of outputs operating at different frequencies with the same supply voltages and equal load conditions. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. NOTE: VDDx denotes VDDA, VDDB, VDDC.
87946AYI
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4
REV. B OCTOBER 22, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS CLOCK GENERATOR
ICS87946I
PARAMETER MEASUREMENT INFORMATION
VDD, VDDx = 1.65V0.15V
SCOPE
Qx
V
DD
x
2
LVCMOS
Qx
V
DD x 2 tsk(o)
Qy
GND = -1.65V0.15V
3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
PART 1 Qx
V
DDx
2.0V
2.0V V
SW I N G
2
0.8V Clock Outputs
PART 2 Qy
0.8V t
R
V
DD x
t
F
2 tsk(pp)
PART-TO-PART SKEW
OUTPUT RISE/FALL TIME
CLK0, CLK1
VDD 2
QAx, QBx, QCx, QDx
VDD x 2 t
PD
Propagation Delay
87946AYI
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5
REV. B OCTOBER 22, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS CLOCK GENERATOR RELIABILITY INFORMATION
ICS87946I
TABLE 6. JAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87946I is: 1204
87946AYI
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REV. B OCTOBER 22, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS CLOCK GENERATOR
ICS87946I
PACKAGE OUTLINE - Y SUFFIX
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L q ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
87946AYI
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7
REV. B OCTOBER 22, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS CLOCK GENERATOR
Marking ICS87946AYI ICS87946AYI Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature -40C to 85C -40C to 85C
ICS87946I
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS87946AYI ICS87946AYIT
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87946AYI
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8
REV. B OCTOBER 22, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS CLOCK GENERATOR
REVISION HISTORY SHEET Description of Change In Features section added Max. Input/Output Frequency bullet. Revised MR/nOE description. Revised Output Rise & Fall Time Diagram. AC Characteristics table - changed (CLK0, CLK1)) tpLH from 6.0ns max. to 12.0ns max., deleted typical value. (CLK0, CLK1)) tpHL from 6.0ns max. to 11.5ns max. , deleted typical value. Date 08/14/02
ICS87946I
Rev A
Table T1
Page 1 2 6
B
T5
4
10/22/02
87946AYI
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REV. B OCTOBER 22, 2002

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